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RTL Training Program
Mastering Digital Circuit Design
Join Our Exclusive 8-Week RTL Training Program
Join our comprehensive 8-week RTL Training Program, tailored for professionals seeking to excel in digital circuit design. Dive deep into the world of Verilog and ASICs with expert-led sessions.
Course Outline
Digital Circuits with Verilog: Learn to create cutting-edge digital circuits using the Verilog synthesizable subset.
Design Process & HDLs: Understand the crucial role of Hardware Description Languages in modern design methodologies.
Simulation Insights: Gain insights into simulation processes, including a focus on VCS (Verilog Compiled Simulator).
ASICs Exploration: Explore various types of Application-Specific Integrated Circuits (ASICs).
Verilog Essentials: Receive a comprehensive overview of Verilog for practical applications.
Circuit Design: Delve into combinatorial and sequential circuits, uncovering the naunces of each.
Coding Styles & Best Practices: Learn coding styles and how to avoid simulation/synthesis mismatches.
Meet your instructors
Faisal Haque
Founder and CEO - Imparé
- Over 30 years of experience in verification and design.
- Key roles at Intel, Cisco, and Qualcomm.
- Co-chaired the SystemVerilog sub-committee and authored three books.
- Developed world-record-setting Cisco CRS-1 router.
Dr. Arshad Riazuddin
Principal Engineer - Imparé
- Over 30 years in high-paced computer systems, IP, and ASIC companies.
- Experience in managing design centers and leading design & verification teams.
- Expertise in HW/SW partitioning and technical support in sales.
What you'll learn
- Master how to create Digital circuits using Verilog Synthesizable subset.
- Learn the design process, the integral role of HDLs, and simulation.
- Get insights into how simulators work, with an introduction to VCS. Also, learn about the different types of ASICs.
- Receive a comprehensive overview of Verilog.
- Learn about combinatorial circuits, followed by sequential circuits.
- Understand coding styles and simulation/synthesis mismatches.
Pre-Requisites
One Year of Digital Logic Design: Solid foundation in digital logic principles.
One Year of C Language: Proficiency in C or equivalent programming experience.
Verilog Familiarity: Basic knowledge of Verilog is expected.
class schedule
Duration: 8 Weeks
Timing: Weekly Classes, 9 AM to 11:30 AM PST
cost of training
Cost of the complete 8 weeks training is USD 399 only
Class Project
As a part of the course, participants will undertake a hands-on project where they will design a 32-bit CPU. This immersive project is not just an exercise but a core part of the learning experience, designed to reinforce the theoretical concepts covered in our curriculum. You'll gain practical experience that goes beyond the classroom, preparing you for real-world engineering tasks.
- Integrate Theory and Practice: Solidify your understanding by designing a 32-bit CPU.
- Hands-on Project: Gain practical experience in CPU architecture and design.
- Project-Based Learning: Enhance learning through a project that mirrors industry practices.
- Showcase Your Expertise: Complete the course with a portfolio-ready project.
Receive a Certificate and Exclusive T-Shirt
Celebrate your success! Complete the course and get a NY State-Licensed Certificate, plus a special edition T-shirt to showcase your achievement. We'll send you details on how to download your certificate and claim your T-shirt. Wear your accomplishment with pride and share it with your network on LinkedIn.
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